Modeling, synthesis and test logic insertion for DLX CPU
121 p.
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2010
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sg-ntu-dr.10356-391482023-07-04T15:03:44Z Modeling, synthesis and test logic insertion for DLX CPU Bandlamudi Kirankumar Jong Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems 121 p. Mixed signal integrated circuits have become common in recent years. In these designs, some circuits are digital functional blocks while others are analog modules. Data processors are one of the widely used modules in present day communication chips and also in DSP designs. Many times, these modules are given by external vendors as IPs. Control circuits are normally designed to control the interface of the digital and analog modules and to configure the internal settings of the chip. Also, the test cost is steadily increasing, since high end test systems are required due to the complexity of the chip and the higher data rates. It is a good idea to have some simple data processing circuits that can do the job of data processing and control the internal resources and operations of integrated circuit with firmware. Master of Science (Integrated Circuit Design) 2010-05-21T04:45:55Z 2010-05-21T04:45:55Z 2007 2007 Thesis http://hdl.handle.net/10356/39148 application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Bandlamudi Kirankumar Modeling, synthesis and test logic insertion for DLX CPU |
| description |
121 p. |
| author2 |
Jong Ching Chuen |
| author_facet |
Jong Ching Chuen Bandlamudi Kirankumar |
| format |
Theses and Dissertations |
| author |
Bandlamudi Kirankumar |
| author_sort |
Bandlamudi Kirankumar |
| title |
Modeling, synthesis and test logic insertion for DLX CPU |
| title_short |
Modeling, synthesis and test logic insertion for DLX CPU |
| title_full |
Modeling, synthesis and test logic insertion for DLX CPU |
| title_fullStr |
Modeling, synthesis and test logic insertion for DLX CPU |
| title_full_unstemmed |
Modeling, synthesis and test logic insertion for DLX CPU |
| title_sort |
modeling, synthesis and test logic insertion for dlx cpu |
| publishDate |
2010 |
| url |
http://hdl.handle.net/10356/39148 |
| _version_ |
1772828949020147712 |