Design of a digital PWM for digital class D amplifiers

• Main Author: Chue, Colin Jian Rong.
• Other Authors: Tan Meng Tong
• Format: Final Year Project
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/40263
• Institution: Nanyang Technological University

This report presents the design of a pulse generator in a Digital Class D Amplifier using Cadence software. The multiplexer, delay cells and counters were first designed prior to the synthesis to obtain the full pulse generator circuit. Digital Pulse Width Modulators (DPWMs) are more prevalent for Class D Amplifier applications. The advantages include elimination of the Digital-to-Analog converter, high power efficiency, noise immunity and ease in implementation over its analog counterpart. There are 4 different types of pulse generators for implementing the pulse generator block of the digital pulse width modulator. In this project, the clock-counter cum tapped-delay-line method was designed using Cadence as this topology compromises between the high power dissipation of the clock-counter and large circuit area of the delay-line. The implementation of the delay cell to form the tapped-delay-line circuit had found that using a flip-flop was the most suitable design as it guaranteed that the duty cycle available at the output will not grow or reduce greatly after every sequence/cycle. Additional delay elements and buffers were included as and where the source of problems occurred, and tuning the counter flip-flop transistor size was done to optimize the output response. Measurement of the output DPWM signal over a period shows that the design specifications are met. The worst case Differential Non Linearity (DNL) was measured and calculated to be +0.859 LSB. Recommendations to the project were to implement a delay locked loop to control the delay of each cell, this in turn will improve the accuracy of the delay cell outputs. The use of differential delay cells in implementation will ensure that the DPWM is insensitive to process variations and reduce phase noise.