Design and implementation of globally asynchronous locally synchronous systems

• Main Author: Tan, Cher Jiun.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/40368
• Institution: Nanyang Technological University

Single-clocked digital systems are largely a thing in the past. Though most digital circuits remain synchronous, many designs feature multiple clock domains, which are often running at different clock frequencies. Moreover, with the advancement of CMOS process technology, many functional blocks can be integrated onto a single die, which further leads to the problems of noise, electromagnetic interference (EMI), and the dominance of the interconnect delay over the gate delay. Communication between the different clock domains are not trivial and must be handled with care. Several schemes can be used to handle the multiple clock domains communication. This report focuses on the pausible-clock globally-asynchronous locally-synchronous (GALS) scheme, which employs the asynchronous communication protocols to decouple the timing issues for the separate locally synchronous (LS) modules, by stopping the local clock (or the LS modules) during each data transfer. The GALS scheme facilitates fast block reuse by providing asynchronous wrapper circuits to handle inter-block communications across clock domain boundaries. An efficient GALS design flow has been developed and implemented on real-life digital signal processing (DSP) system – the FIR filters. Results show that the proposed asynchronous port controllers are able to function correctly under several clock domains. In 50 MHz – 30 MHz clock domains, the asynchronous wrapper consumed only about 0.82 % of the total power consumption and 0.4 % of the total resources by the FIR GALS system. Detailed comparisons with the Avalon interface using Altera SOPC Builder for multiple clock domains design are also reported. The asynchronous wrapper shows slightly lower latency and power consumption compared to the dual-clock FIFO of the Avalon interface. Further improvements on the asynchronous wrapper are suggested to overcome the slight overhead penalty and low throughput. Though the current reported design has some limitations, however with further test and verification in future, the GALS approach would be a great alternative solution to the multiple clock domains (MCD) design, and could reduce the dependency on the Avalon interface, which is only limited to the Altera‟s modules.