An ultra low-power precision sample-and-hold circuit for biomedical application

• Main Author: Mah, Sai Lei
• Other Authors: Chan Pak Kwong
• Format: Final Year Project
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/40448
• Institution: Nanyang Technological University

In this project, the student was able to realize a low-power precision sample-and-hold (S/H) circuit for biomedical application based on switched-capacitor circuit. The performance of the circuit in this work is comparable with some previously published works on precision S/H circuits. The S/H circuit was designed to work with a supply voltage of 1.8V and was realized in 0.18 μm CMOS technology. The S/H circuit was developed from a capacitive-reset gain switched-capacitor circuit that has benefits of insensitive to op-amp input offset, finite open-loop gain of op-amp, low power and rail-to-rail characteristic. Capacitor-mismatch compensation was then incorporated into it to make the circuit insensitive to capacitor mismatch. In response to intentionally introduced 2% of capacitor mismatch, output of the new circuit only changes by a few micro-percent with respect to that of circuit without any intentionally introduced capacitor mismatch. The parameters that were used to check the precision of the S/H circuit are hold pedestal and total harmonic distortion. In the end, the student managed to achieve hold-pedestal less than 0.081 mV and -76 dB of total harmonic distortion that corresponds to 12.62 bits of ENOB in response to 1-Vpp and 1-kHz sinusoidal input at 128 kHz of sampling frequency. Operational amplifier (op-amp) used in the circuit plays a major part in contributing to the power consumption of the circuit. Thus, student has focused on reducing power consumption of the op-amp. With a target of achieving less than 13 μW of power consumption, some transistors in the op-amp may works in moderate or weak inversion. At last, the student managed to design an op-amp that consumes 12.04 μW that gives 0.395 μW/pF of power efficiency. The Figure of Merits achieved is 8.30×10-3 μA/MHz.