FPGA-based multi-rate system design : Avalon Interface vs.Globally Asynchronous Locally Synchronous approach

• Main Author: Zou, You.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/40541
• Institution: Nanyang Technological University

Avalon Interfaces is developed by Altera and it allows fast and convenient interfacing between Altera IP cores, which are also called components. Avalon Interfaces are widely used inside System-on-a-Programmable Chip (SOPC) Builder, which is a design tool and environment embedded inside Altera Quartus II. SOPC Builder enables fast system integration by using Avalon interface. Avalon interface greatly relieves the design efforts for interfacing various components operating under different clock domains inside one system, namely Multiple Clock Domain (MCD) systems. The SOPC Builder has now been widely adopted for fast prototyping of Digital Signal Processing (DSP) systems. On the other hand, Globally Asynchronous Locally Synchronous (GALS) architecture is another design method for building MCD systems. In this project, only those MCD systems which use pure asynchronous interfaces such as pausible clock interface are considered as GALS systems. The author has built, simulated, implemented and verified a MCD DSP system comprising of two Finite Impulse Response (FIR) filters using Altera SOPC Builder. The author has then investigated, analyzed and compared the system with another DSP system consisting of the same components and configuration but based on GALS approach or, more specifically, the pausible clock architecture, which is designed and built by another final year undergraduate student. It has been found that the Altera SOPC Builder approach outweighs the GALS (plausible clock) approach obviously in terms of the design efforts, throughput (29.3% higher) and area (37% smaller); however, the GALS (plausible clock) approach consumes less power by an insignificant amount (4.85% less) with a slightly smaller latency (5.7% smaller). At last, based on the comparison of the two systems, it is concluded that in spite of low design flexibility and some other limitations, SOPC Builder fits best in the circumstances of developing robust DSP systems in a short design period. On the other hand, the potential for GALS (pausible clock) approach in power consumption reduction should also be paid special attention to. It can be expected that the GALS approach will be greatly favored for low power designs in the future, provided a breakthrough in its power consumption saving capability as well as the design easiness.