Methods for rapid selection of processors for constraint-aware embedded systems

• Main Author: Abhijit Ray
• Other Authors: Thambipillai Srikanthan
• Format: Theses and Dissertations
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Computer science and engineering::Computer systems organization
• Online Access: https://hdl.handle.net/10356/41131
• Institution: Nanyang Technological University

Embedded systems design is moving from ASIC based implementations to us-ing commercial off the shelf processors. ASICs tend to have long design cycles and they do not offer much flexibility for later design changes. With the rapid advances in embedded systems and microprocessor technology, the traditional methods of selecting a processor for an embedded system may not be effective. The techniques have to keep up with the advanced novel architectures that are constantly being developed. Processor selection is an important part of embedded system design. The current methods of performance evaluation which are mostly based on instruction sets simulators are quite accurate but they suffer from the drawback of consuming large amounts of time. Moreover, as processor technology improves, the construction of such instruction set simulators becomes more complex. Hence, with advances in technology, the evaluation process becomes slower.Therefore to speedup the process , a higher level view of the underlying architecture is desirable.Estimation, instead of a detailed performance evaluation, can help in narrowing down the choice to a smaller set of processors. Fast processor performance estimation can easily lead to large saving in design time.Estimation at a higher level does incur the cost of decrease in accuracy. But this disadvantage is easily compensated for by the increase in estimation speed, thereby allowing us to take into consideration more processors.