Low power reconfigurable receiver architectures for migrating software defined radio technology from base stations to handsets

• Main Author: Vinod Achutavarrier Prasad
• Other Authors: School of Computer Engineering
• Format: Research Report
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Wireless communication systems
• Online Access: http://hdl.handle.net/10356/42329
• Institution: Nanyang Technological University

The objective of this research project is to develop low power reconfigurable receiver architectures for migrating Software Defined Radio (SDR) technology from base stations to handsets. We address the issues related to the additional area and power constraints imposed by the resource-constrained handsets, which is a major design challenge in migrating SDR from base stations to handsets. Concepts from the generalized sampling theory for non-bandlimited signals has been combined with the theory for sampling signals with finite rate of innovation to study the minimum sampling rate requirements for signals in shift invariant spaces. We have established the formal relationship between the rate of innovation of the signal and the sampling kernel for perfect reconstruction. We showed through some examples that our proposed method to calculate the rate of innovation is accurate and the way to identify a suitable sampling kernel to achieve minimum sampling is valid. Our further work focused on proposing new low complexity architectures for SDR channelizer, which is the most computationally intensive block in the digital front-end. We have proposed a new Common Subexpression Elimination (CSE) technique based on binary representation of filter coefficients which resulted in better reduction of channel filter complexity than existing methods proposed in literature. The proposed CSE method produces filters with fewer adders without increasing the delay. New methodologies have been developed for the design of reduced complexity high-speed digital filters. The methods are applicable to other relevant digital signal processing problems that can be transformed to a MCM model. A new Hamming Weight Pyramid (HWP) analytical structure has been proposed to analyze the properties of canonical signed digit (CSD) numbers. These properties have been exploited to develop elegant algorithm for the direct conversion of decimal number to CSD form, and overcome the limit imposed on n-Dimensional Reduced Adder Graph (RAG-n) algorithm.