Reducing cell jitter in a input-buffered crossbar ATM switch

• Main Author: Tan, Ching Wai.
• Other Authors: Lee Bu Sung
• Format: Theses and Dissertations
• Language: English
• Published: 2010
• Subjects: DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
• Online Access: http://hdl.handle.net/10356/42561
• Institution: Nanyang Technological University

In this dissertation, an introduction to the Asynchronous Transfer Mode (ATM) technology is given. Several performance issues pertaining to ATM networks are also described. One particular performance metric that is of interest in this project is cell jitter. The main objective of this project is to investigate the architecture of an ATM switch, the DEC GigaSwitch, and research into ways to improve the average cell jitter of cells passing through this switch. Introductory work in this project includes the study of the internal architecture of the DEC GigaSwitch. This dissertation therefore includes an overview of ATM switches in general, followed by a description of the GigaSwitch architecture. Central to the discussion of the GigaSwitch architecture is the Time Division Multiplexing (TDM) scheduling frame. The TDM frame consists of 1024 time slots; a time slot is the unit of time for transfer of an ATM cell from an input port to an output port of the switch. For each CBR connection, the GigaSwitch allocates a certain number of time slots for the transmission of the CBR cells. Slots that are not allocated to CBR connections can be used for transmission of non-CBR cells, such as those of ABR connections.