Low power continuous-time sigma delta modulator
The rapidly growing market for portable electronic systems such as wireless communication devices or battery powered electronic devices increases the demand for low-voltage and low-power circuits and building blocks. Reducing the power dissipation in integrated circuits is required to minim...
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sg-ntu-dr.10356-438762023-07-04T16:10:08Z Low power continuous-time sigma delta modulator Teh, Li Lian. Siek Liter School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits The rapidly growing market for portable electronic systems such as wireless communication devices or battery powered electronic devices increases the demand for low-voltage and low-power circuits and building blocks. Reducing the power dissipation in integrated circuits is required to minimize the recharging cycles or to extend the battery lifetime as much as possible. This work presents the realization of a continuous-time (CT) sigma-delta (Σ?) analog-to-digital converter (ADC) that can achieve 87dB SNRP, 85dB SNDR and 90dB DR with 3.2MS/s output data rate at 1.5V supply using the 1.8V/0.18μm CMOS process. A fully differential 4th-order single-loop, single-bit modulator is employed in this work to provide sufficient noise shaping for the quantization noise and internal sampling error. Several system and circuit design techniques have been utilized which aim to achieve high resolution, low power consumption CT Σ? ADC. Cascaded integrators with feedfoward summation are chosen to implement the loop filter since it is more power efficient. Return-to-zero (RZ) feedback digital-to-analog converters (DACs) is employed to reduce the inter-symbol interference (ISI) problems which would otherwise degrade the modulator linearity and hence the maximum achievable signal-to-noise ratio (SNR). Single-loop architecture is used to relax the matching requirement of the loop filter which is suitable for a 14-bit high resolution ADC. By combining different techniques to address various design challenges, the modulator consumes only 207OW with 3.2MHz sampling rate and the entire die occupies 1.725mm2. die chip area including pads. Master of Engineering 2011-05-09T02:40:36Z 2011-05-09T02:40:36Z 2011 2011 Thesis http://hdl.handle.net/10356/43876 en 150 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Teh, Li Lian. Low power continuous-time sigma delta modulator |
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The rapidly growing market for portable electronic systems such as wireless
communication devices or battery powered electronic devices increases the demand for
low-voltage and low-power circuits and building blocks. Reducing the power dissipation
in integrated circuits is required to minimize the recharging cycles or to extend the battery
lifetime as much as possible.
This work presents the realization of a continuous-time (CT) sigma-delta (Σ?)
analog-to-digital converter (ADC) that can achieve 87dB SNRP, 85dB SNDR and 90dB
DR with 3.2MS/s output data rate at 1.5V supply using the 1.8V/0.18μm CMOS process.
A fully differential 4th-order single-loop, single-bit modulator is employed in this work to
provide sufficient noise shaping for the quantization noise and internal sampling error.
Several system and circuit design techniques have been utilized which aim to achieve
high resolution, low power consumption CT Σ? ADC. Cascaded integrators with
feedfoward summation are chosen to implement the loop filter since it is more power
efficient. Return-to-zero (RZ) feedback digital-to-analog converters (DACs) is employed
to reduce the inter-symbol interference (ISI) problems which would otherwise degrade the
modulator linearity and hence the maximum achievable signal-to-noise ratio (SNR).
Single-loop architecture is used to relax the matching requirement of the loop filter which
is suitable for a 14-bit high resolution ADC. By combining different techniques to address
various design challenges, the modulator consumes only 207OW with 3.2MHz sampling
rate and the entire die occupies 1.725mm2. die chip area including pads. |
author2 |
Siek Liter |
author_facet |
Siek Liter Teh, Li Lian. |
format |
Theses and Dissertations |
author |
Teh, Li Lian. |
author_sort |
Teh, Li Lian. |
title |
Low power continuous-time sigma delta modulator |
title_short |
Low power continuous-time sigma delta modulator |
title_full |
Low power continuous-time sigma delta modulator |
title_fullStr |
Low power continuous-time sigma delta modulator |
title_full_unstemmed |
Low power continuous-time sigma delta modulator |
title_sort |
low power continuous-time sigma delta modulator |
publishDate |
2011 |
url |
http://hdl.handle.net/10356/43876 |
_version_ |
1772827831349280768 |