Building carbon chips : graphene-based circuit design

• Main Author: Leong, Mang Yew.
• Other Authors: School of Computer Engineering
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Computer science and engineering::Hardware::Integrated circuits
• Online Access: http://hdl.handle.net/10356/44151
• Institution: Nanyang Technological University

This report reviews that graphene can be the potential candidate for a technology advancement because of its extraordinary physical properties. After taking through the basic types of Graphene Nanoribbon (GNR), which is a thin sheet of graphene, fabrication techniques are introduced. GNR interconnect design based on equivalent circuit design are presented and compared with copper (Cu). In order for GNR to be comparable or better than Cu as interconnect, intercalation doping and high edge-specularity must be achieved and taken into consideration, as well as Fermi energy level and edge roughness level that will increase resistance when modelling GNR interconnect Resistance and capacitance of GNR must also be well calculated to be accurate in the conclusion of result. Comparison of BSIM4 MOSFET CMOS logic gates are done against modelled graphene field-effect transistor (GFET) CMOS logic gates via I-V SPICE. Results show that GFET is significantly better in terms of output delay, however having higher power dissipation leads to a need of implementing power management for applications using GFET. Graphene can be a promising material for electronic systems but theoretical factors such as gate current leakage must be considered to deliver accurate result.