State-of-the-art VCO design

• Main Author: Gao, Yuan.
• Other Authors: Boon Chirn Chye
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/44932
• Institution: Nanyang Technological University

The designs of Voltage Controlled Oscillators (VCO) are explored in this project in a standard RF 65nm CMOS technology. Four different VCOs (A, B, C and D) are designed and compared to discuss the advantages of PMOS transistors and capacitive cross-coupled feedback. With the contract of NMOS, the oscillators built with PMOS transistors have an improvement about 5dB phase noise. However, due to the lager parasitic capacitance of PMOS, the VCOs, which employ PMOS as their core transistors, achieve relatively lower frequencies. In addition, the capacitive feedback in a VCO can provide a favorable condition for the maximum amplitude. This improvement of phase noise can be obvious in the case of PMOS VCOs. But the disadvantage of capacitive feedback is that the large fixed capacitors in the circuits decreasing the oscillating frequency and tuning range. For the employment of PMOS, Design A with capacitive feedback can generate 41GHz, and display -99.5dBc/Hz @1MHz and -120.07dBc/Hz @10MHz. While there is no capacitor in the feedback of Design B, the oscillator having 51GHz frequency obtains -95.85dBc/Hz @1MHz and -116dBc/Hz @10MHz. For the employment of NMOS, Design C with 48GHz has the phase noise of -89.38 @1MHz and -111.4dBc/Hz @10MHz. Design D achieving 66GHz frequency has the phase noise of -91.96dBc/Hz @1MHz and -114.5dBc/Hz @10MHz.