Design and analysis of low-power, variation-tolerant match-line sense amplifiers for large capacity content addressable memories (CAMs) in 65 nm CMOS process
Content Addressable Memory (CAM) is extensively used in many high speed data searching applications due to its high speed and single clock cycle throughput characteristics. However, this comes at a cost of high power consumption mainly due to the match line sense amplifier. Therefore, a lot of works...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2011
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| 在線閱讀: | http://hdl.handle.net/10356/45740 |
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| 總結: | Content Addressable Memory (CAM) is extensively used in many high speed data searching applications due to its high speed and single clock cycle throughput characteristics. However, this comes at a cost of high power consumption mainly due to the match line sense amplifier. Therefore, a lot of works have been done to reduce the power consumption of the match line sense amplifiers. This report first presents detail analysis designs of CAM Match line sense amplifier designs in 65 nm process technologies. Despite of the power consumptions, their robustness in consideration of process, supply voltage, and temperatures variations is explored in detail. The simulation results show that the conventional design [1] is robust but with a very high power consumption; the pre-charge low sensing techniques including the current-race [2], the ML-stability [3], and the positive-feedback [4] are quite sensitive to external environment variations despite of their low power consumptions; the low-voltage swing sense amplifier design, namely, the charge-injection [5] is very robust while maintaining a very low power consumption. |
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