Adiabatic comparator for analog-to-digital converter (ADC)

• Main Author: Sanket Gupta.
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/45776
• Institution: Nanyang Technological University

This report presents the summary of the work done during the Final Year Project titled “Adiabatic Comparator for Analog-to-Digital Converter” in the year 2010-11. At the moment, there are various applications of ADC. Also, there are various applications which require ultra low power like pacemakers and sensors. Since comparator is the major power guzzling component of an ADC, there is a high demand of low-power comparator. This project presents an adiabatic comparator with ultra-low power to be used in a fully adiabatic SAR ADC for such applications. A low-offset Double-Tail Latch-type Adiabatic Comparator is proposed in a 0.18 μm fabrication technology. The specifications of the comparator meet the requirements for a SAR ADC operating at a voltage of 1V at 1 MHz and with 10 bit resolution of the ADC. The power consumption of the circuit is 7.5 nW at 1MHz clock and 0.25 us charging and discharging period of the resonant power supply (RPS). The delay of the circuit is below 10ns. The layout of the proposed schematic is also presented. Furthermore, the implementation of the comparator under adiabatic technique is shown. The proposed adiabatic comparator can be used with the ACCR DAC to form critical adiabatic components in the SAR ADC. In future, it is hoped that the proposed design of the adiabatic comparator be combined into a fully adiabatic ADC for the aforementioned ultra-low power applications.