Design of a low-voltage CMOS analogue multiplier
The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing...
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sg-ntu-dr.10356-45982023-07-04T15:58:16Z Design of a low-voltage CMOS analogue multiplier Leow, Hee Boon. Siek, Liter School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing of more than lOmV. Its' main application is primarily used for voice signal processing. Master of Science (Integrated Circuit Design) 2008-09-17T09:55:03Z 2008-09-17T09:55:03Z 2005 2005 Thesis http://hdl.handle.net/10356/4598 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Leow, Hee Boon. Design of a low-voltage CMOS analogue multiplier |
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The objective of this project is to design a low-voltage analogue multiplier operating on a 1.3V voltage supply and its' 3-dB bandwidth is expected to be about 100 KHz. This multiplier should be able to operate with the input signals of the 1.2V voltage swing and expect an output voltage swing of more than lOmV. Its' main application is primarily used for voice signal processing. |
| author2 |
Siek, Liter |
| author_facet |
Siek, Liter Leow, Hee Boon. |
| format |
Theses and Dissertations |
| author |
Leow, Hee Boon. |
| author_sort |
Leow, Hee Boon. |
| title |
Design of a low-voltage CMOS analogue multiplier |
| title_short |
Design of a low-voltage CMOS analogue multiplier |
| title_full |
Design of a low-voltage CMOS analogue multiplier |
| title_fullStr |
Design of a low-voltage CMOS analogue multiplier |
| title_full_unstemmed |
Design of a low-voltage CMOS analogue multiplier |
| title_sort |
design of a low-voltage cmos analogue multiplier |
| publishDate |
2008 |
| url |
http://hdl.handle.net/10356/4598 |
| _version_ |
1772826712996839424 |