Design of circuit extractor for VLSI IC design

• Main Author: Soe May Thu Lwin.
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/46178
• Institution: Nanyang Technological University

The title of this final year project is “Design of Circuit Extractor for VLSI IC Design”. To analyze the functionality of a fabricated Integrated Circuit (IC), a common approach is to partition the circuit into many sub-circuits before analyzing the functionality of individual sub-circuit. The connectivity of a circuit is usually described in the netlist. In current industry, one of the ways to generate the netlist from the image of a fabricated IC is to use reversed Electronic Design Automation (EDA) softwares. There is a company named Cellix which provides reversed EDA software tools to generate the netlist. The netlist from Cellix Company was used as the input for the project. The objective of this project is to analyze the functionality of an ill-defined netlist. Since the netlist is ill-defined, the functionality of IC could not be analyzed directly from the netlist. Therefore decomposition of the netlist had been done as the first major step to approach the objective. Followed by association analysis on connected components with analog and digital modules, the second major step had been presented in this report. To accomplish two major steps in a systematical manner, steps by steps procedures had been carried out and they had been described in this report with numerous figures. In addition, the results obtained at the end of each step had been discussed with tables in this report.