60GHz divider design

• Main Author: Tay, Wei Shi.
• Other Authors: Boon Chirn Chye
• Format: Final Year Project
• Language: English
• Published: 2011
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/46499
• Institution: Nanyang Technological University

The opening up of the 57GHz - 64GHz un-channelized spectrum for license-free operation in 2001 prompted intensive effort in developing Radio Frequency integrated circuits and systems operating at the Giga-hertz range. Rapid evolution of the low-cost submicrometer CMOS process technology has aided in the development of more compact, lower power, higher speed and wider bandwidth millimeter-wave applications. Phase-locked loop circuits are extensively used in many communication applications and to keep pace with the rapid evolution in the communication industry, this project was intended to study the various high frequency divider topologies available. The emphasis of this project is to design a low power 60GHz frequency divider. Previous research and finding have strongly supported the feasibility of this project. A 60GHz Injection-locked frequency divider was design in TSMC 65nm CMOS process with locking range of 58.9 – 60.5 GHz and consumes 1.57mW power from a 0.8V supply.