Test methods for gals processor
58 p.
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sg-ntu-dr.10356-468412023-07-04T16:03:10Z Test methods for gals processor Ye Myat Thu. Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits 58 p. As the feature size of the transistor gate reduces, the on-chip clock frequency can increase. The circuit design with conventional synchronous design method becomes a challenging task with regards to clock distribution and skew, especially at high clock frequencies. Furthermore, the power delivery and noise issues become more severe. A fully asynchronous design method could overcome these problems but suffers from significant overhead in terms of execution time and hardware. Moreover, the asynchronous design suffers the lack of design tools. The GALS based approach partitions the system into synchronous modules and uses a handshake protocol for communications. Hence, GALS uses a divide-and-conquer approach that significantly improves the design efficiency [12]. The synchronous modules are encapsulated in order to further reduce the complexity. Master of Science (Electronics) 2011-12-23T10:00:10Z 2011-12-23T10:00:10Z 2010 2010 Thesis http://hdl.handle.net/10356/46841 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Ye Myat Thu. Test methods for gals processor |
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58 p. |
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Gwee Bah Hwee |
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Gwee Bah Hwee Ye Myat Thu. |
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Theses and Dissertations |
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Ye Myat Thu. |
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Ye Myat Thu. |
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Test methods for gals processor |
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Test methods for gals processor |
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Test methods for gals processor |
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Test methods for gals processor |
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Test methods for gals processor |
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test methods for gals processor |
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2011 |
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http://hdl.handle.net/10356/46841 |
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