Constraint-based watermarking techniques for VLSI IP protection
172 p.
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2011
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sg-ntu-dr.10356-469832023-07-04T16:18:43Z Constraint-based watermarking techniques for VLSI IP protection Cui, Aijiao Chang Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems 172 p. With the increase, in the popularity of reusable intellectual property (IP) cores for System-on-a-Chip (SoC), piracy is also on the rise in this new design area. The lure of getting a new product ahead of the competitor at a fraction of, or at no cost, is often too much a temptation to ignore, which results in an increasingly buoyant IP theft. To safeguard the IP owner against piracy and illegal redistribution of the IP cores, constraint-based watermarking has been used as a pivotal technology to protect the copyright of the very large scale integration (VLSI) IPs. In this thesis, a comprehensive framework of constraint-based watermarking techniques has been studied and explored at different design abstraction levels. The goal is to develop robust watermarking chemes and techniques for VLSI IP protection that can facilitate easy detection and tracking of IP misappropriation. DOCTOR OF PHILOSOPHY (EEE) 2011-12-27T05:51:58Z 2011-12-27T05:51:58Z 2009 2009 Thesis Cui, A. (2009). Constraint-based watermarking techniques for VLSI IP protection. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/46983 10.32657/10356/46983 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Cui, Aijiao Constraint-based watermarking techniques for VLSI IP protection |
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172 p. |
author2 |
Chang Chip Hong |
author_facet |
Chang Chip Hong Cui, Aijiao |
format |
Theses and Dissertations |
author |
Cui, Aijiao |
author_sort |
Cui, Aijiao |
title |
Constraint-based watermarking techniques for VLSI IP protection |
title_short |
Constraint-based watermarking techniques for VLSI IP protection |
title_full |
Constraint-based watermarking techniques for VLSI IP protection |
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Constraint-based watermarking techniques for VLSI IP protection |
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Constraint-based watermarking techniques for VLSI IP protection |
title_sort |
constraint-based watermarking techniques for vlsi ip protection |
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2011 |
url |
https://hdl.handle.net/10356/46983 |
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1772828791262937088 |