Development of Viterbi decoder in VHDL
This reprt briefly introduces the theory of Viterbi algorithm for both hard decision and soft decision decoding and mainly focuses on the design and implementation of the soft decision Viterbi decoder by using VHDL, one of the most popular register transfer level language for the hardware design.
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| Format: | Theses and Dissertations |
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2008
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| Online Access: | http://hdl.handle.net/10356/4732 |
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| Institution: | Nanyang Technological University |
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sg-ntu-dr.10356-47322023-07-04T15:06:41Z Development of Viterbi decoder in VHDL Liu, Jun. Chua, Tai Wei School of Electrical and Electronic Engineering DRNTU::Engineering::Computer science and engineering::Hardware This reprt briefly introduces the theory of Viterbi algorithm for both hard decision and soft decision decoding and mainly focuses on the design and implementation of the soft decision Viterbi decoder by using VHDL, one of the most popular register transfer level language for the hardware design. Master of Science (Communications Engineering) 2008-09-17T09:57:30Z 2008-09-17T09:57:30Z 2003 2003 Thesis http://hdl.handle.net/10356/4732 Nanyang Technological University application/pdf |
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Nanyang Technological University |
| building |
NTU Library |
| continent |
Asia |
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Singapore Singapore |
| content_provider |
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DR-NTU |
| topic |
DRNTU::Engineering::Computer science and engineering::Hardware |
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DRNTU::Engineering::Computer science and engineering::Hardware Liu, Jun. Development of Viterbi decoder in VHDL |
| description |
This reprt briefly introduces the theory of Viterbi algorithm for both hard decision and soft decision decoding and mainly focuses on the design and implementation of the soft decision Viterbi decoder by using VHDL, one of the most popular register transfer level language for the hardware design. |
| author2 |
Chua, Tai Wei |
| author_facet |
Chua, Tai Wei Liu, Jun. |
| format |
Theses and Dissertations |
| author |
Liu, Jun. |
| author_sort |
Liu, Jun. |
| title |
Development of Viterbi decoder in VHDL |
| title_short |
Development of Viterbi decoder in VHDL |
| title_full |
Development of Viterbi decoder in VHDL |
| title_fullStr |
Development of Viterbi decoder in VHDL |
| title_full_unstemmed |
Development of Viterbi decoder in VHDL |
| title_sort |
development of viterbi decoder in vhdl |
| publishDate |
2008 |
| url |
http://hdl.handle.net/10356/4732 |
| _version_ |
1772826828866584576 |