Low power FFT processor IC
A low voltage low power FFT processor has been designed to meet the specifications required for application in an advance digital hearing enhancement device. This thesis will discuss the design, implementation and analysis of the proposed FFT processor. The processor is designed and implemented as a...
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2008
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| Institution: | Nanyang Technological University |
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sg-ntu-dr.10356-48182023-07-04T15:46:02Z Low power FFT processor IC Loy, Teck Pui. Gwee, Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits A low voltage low power FFT processor has been designed to meet the specifications required for application in an advance digital hearing enhancement device. This thesis will discuss the design, implementation and analysis of the proposed FFT processor. The processor is designed and implemented as a 128 point FFT processor. It operates with a supply voltage of 1.1V at a system frequency of 1MHz. The processor is implemented using a pipelined architecture and utilizes a radix-2 decimation in time FFT algorithm. This configuration is expected to deliver a design with the least power dissipation for the required specification. Master of Science (Integrated Circuit Design) 2008-09-17T09:59:18Z 2008-09-17T09:59:18Z 2004 2004 Thesis http://hdl.handle.net/10356/4818 Nanyang Technological University application/pdf |
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Singapore Singapore |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Loy, Teck Pui. Low power FFT processor IC |
| description |
A low voltage low power FFT processor has been designed to meet the specifications required for application in an advance digital hearing enhancement device. This thesis will discuss the design, implementation and analysis of the proposed FFT processor. The processor is designed and implemented as a 128 point FFT processor. It operates with a supply voltage of 1.1V at a system frequency of 1MHz. The processor is implemented using a pipelined architecture and utilizes a radix-2 decimation in time FFT algorithm. This configuration is expected to deliver a design with the least power dissipation for the required specification. |
| author2 |
Gwee, Bah Hwee |
| author_facet |
Gwee, Bah Hwee Loy, Teck Pui. |
| format |
Theses and Dissertations |
| author |
Loy, Teck Pui. |
| author_sort |
Loy, Teck Pui. |
| title |
Low power FFT processor IC |
| title_short |
Low power FFT processor IC |
| title_full |
Low power FFT processor IC |
| title_fullStr |
Low power FFT processor IC |
| title_full_unstemmed |
Low power FFT processor IC |
| title_sort |
low power fft processor ic |
| publishDate |
2008 |
| url |
http://hdl.handle.net/10356/4818 |
| _version_ |
1772826962394349568 |