Design of an area efficient subthreshold SRAM cell

• Main Author: Nguyen, Truc Quynh.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Final Year Project
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: http://hdl.handle.net/10356/50093
• Institution: Nanyang Technological University

This report focuses on Static Random Access Memory (SRAM). There are three main parts that will be discussed in details. First part touches on the very fundamentals of SRAM including various cell structures and their improvements in performance as well as tradeoffs. Following up is the simulation to perform cell analysis for two particular structures: 6T SRAM and 10T SRAM. In second part, the techniques to improve the read bitline swing based on 8T cell structure. Conventional 8T will be analyzed in order to compare with the modifications such as different configuration for read port, 8T cell with footer and 8T bitline with compensation current. As a result of the modification, a constant bitline swing is achieved providing a large sensing window. This is obtained by the compensation current technique which also limits the area overhead. All the analysis and ideas are verified by simulation data. In the last part, it will discuss a peripheral circuit: row decoder where both schematic design and layout will be introduced.