Ultra low-power low-noise amplifier designs for 2.4 GHz ISM band applications

• Main Author: Tran, Thi Thu Nga
• Other Authors: Boon Chirn Chye
• Format: Theses and Dissertations
• Language: English
• Published: 2012
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/50790
• Institution: Nanyang Technological University

The wireless communication industry is currently experiencing tremendous growth. In responding to the demand for a low-cost but high performance wireless front-end, many intensive researches on CMOS radio-frequency (RF) front-end circuits have been carried out. The ultimate goal is to minimize the trade-off between high performance and low-cost, low power consumption design. Low noise amplifier (LNA) is typically the first stage of a receiver. Its performance greatly affects the overall receiver performance. In this thesis, four LNAs are proposed. They are designed for the IEEE 802.15.4 standard in the 2.4 GHz ISM band. The first three LNAs are optimized for low NF and low power. An application of this type of LNA is to be used as the amplification stage before the active mixer in the receiver chain . Active mixer provides active gain while consuming some dc power. Therefore the LNA's gain requirement can be relaxed. But its power consumption needs to be low to compensate for the power consumption from the active mixer. With a relaxed gain, the LNA should have good NF to avoid degrading the overall receiver NF. The fourth LNA is optimized for high gain. This optimization is useful in the receiver system where passive mixer is used for frequency conversion. Passive mixer consumes no dc power while having some conversion loss. Therefore, high LNA gain is required in this type of system.There are four important contributions in this research. Firstly, and LNA (LNA1) that combining the merits of the inductive source degeneration common-source LNA (L-CSLNA) and the common-gate LNA (CGLNA) is introduced. The proposed LNA1 is a fully differential gm-boosting CGLNA with series inductor input matching network that improves the NF. The circuit's input matching, NF and gain have been derived to verify the design methodology. The LNA was designed and fabricated using 0.18 μm CMOS technology. It consumes only 0.98 mA from 1.0 V power supply and achieves a measured gain of 15 dB and NF of 5 dB. The series inductor input matching CGLNA is attractive for low-power fully integrated applications in CMOS technologies. Even though the high NF problem of the CGLNA has been addressed in the proposed LNA1, we wish to further reduce the NF to achieve better trade-off between NF and power consumption. LNA2 was designed with a simple but effective noise-reducing technique. An inductor was added in parallel to the input transistor to reduce the noise from both the cascode and the input transistor. The LNA's input matching, NF and gain have been derived to verify the design methodology. The LNA achieves a measured gain of 14.8 dB, NF of 4.5 dB and IIP3 of -5.7dBm respectively. It consumes only 0.95 mW from a 1.0 V supply voltage.