Class-D amplifier

• Main Author: Kang, Yang.
• Other Authors: Chang, Joseph Sylvester
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/52635
• Institution: Nanyang Technological University

This Final Year Project pertains to the design of audio analog Class D amplifiers (CDAs) with emphases on low distortion and high power-efficiency, including low-voltage (2.4V) single-ended and fully-differential CDAs and the output stage of a high-voltage (24V) CDA. Five contributions are made in this FYP. First, the effect of the comparator delay on the distortion of the CDAs is investigated. From the two designed comparators, we show that reducing the comparator delay from 30ns to 2ns improves the total harmonic distortion(THD) of the single-ended CDA from ~0.1% to 0.01694% at the cost of slightly reduced power-efficiency; the degree of improvement for the fully-differential CDA is similar. The comparator with the shorted delay is designed, taped out and will be measured (after fabrication). Second, the design of two carrier generators, op-amp based and switched-current, is investigated and compared. We ascertained that the op-amp based carrier generator not only required a large IC area but the tuning of carrier frequency is undesirably fixed (by the passive components thereof). We infered that the switched-current counterpart is preferred, and this design is completed, taped out and will be measured (after fabrication). Third, the design of two differential op-amps, a fully-differential op-amp with common mode feedback and another comprising two single-ended op-amps, for the fully-differential CDA is investigated. We show that the employment of the fully-differential op-amp results in lower THD of the CDA. The fully-differential op-amp with common mode feedback is designed. Fourth, two output stages, NMOS-NMOS and PMOS-NMOS configurations, for the high voltage (24V) CDA is investigated and compared. We inferred that PMOS-NMOS configuration is advantageous, particularly for overcoming the low gate breakdown voltage (~3.5V) problem but at the cost of larger layout area (~2x). The PMOS-NMOS output stage features a power-efficiency of 95% across a large range of modulation indexes and can deliver power up to 30W. Fifth, the two aforesaid CDAs (2.4 single-ended and fully-differential) and the 24V CDA output stage are designed, and their THD and power-efficiency are compared. These attributes are tabulated below. Of specific interest, the attributes of the 2.4V fully-differential CDA exceed state-of-the-art deisgn, while the other two designs are comparable to state-of-the-art. In conclusion, the design of two low-voltage (2.4V) CDAs with emphases on low distortion and high power-efficiency and the output stage of a high-voltage CDA have been successfully designed, with the three key building blocks of the CDA taped-out.