Design a test circuit using altium designer

The process of planning and designing of a Printed Circuit Board (PCB) used in testing an IC chip with a footprint of DIP 40, designed by a PhD student, is presented in this report. Firstly, the IC chip is being studied in this project and its features, such as the voltage requirements and the numbe...

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Bibliographic Details
Main Author: Ng, Shun Qiang.
Other Authors: Jong Ching Chuen
Format: Final Year Project
Language:English
Published: 2013
Subjects:
Online Access:http://hdl.handle.net/10356/53344
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Institution: Nanyang Technological University
Language: English
Description
Summary:The process of planning and designing of a Printed Circuit Board (PCB) used in testing an IC chip with a footprint of DIP 40, designed by a PhD student, is presented in this report. Firstly, the IC chip is being studied in this project and its features, such as the voltage requirements and the number of inputs and outputs, were outlined in this report. An alternate testing unit was also chosen and discussed. A software named Altium Designer is being used for the designing and creating of the PCB. This software is evaluated in this project and the procedure of creating the test circuit, creating the components, drawing of the schematic, components placement and routing, validation, as well as fabrication output files is presented. Also, the various functions of the Altium Designer such as the auto routing capability, interactive routing capability, design rule checking and multi-sheet design will be highlighted. The PCB design has incorporated many discrete components and they are: voltage regulators, decoupling capacitors, clock implementation, current sense amplifier, field programmable gate array. All the components are being presented in this report. On top of that, there are also external equipment involved and they are: DC power supply, pulse generator, and oscilloscope. The challenges of implementing a high clocking frequency of 350 MHz and the measuring of current at a particular clock cycle into the chip will be presented together with the solutions in the later part of the report.