Design of a CMOS dynamic reference ADC
This report describes a detailed approach to design an 8-bit dynamic reference analog-to-digital converter (ADC). The converter is designed based on the Charter 0.18 um processing technology. The design tools used in the project are Cadence Virtuoso schematic editor and Virtuoso Analog Design Enviro...
Saved in:
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/53409 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | This report describes a detailed approach to design an 8-bit dynamic reference analog-to-digital converter (ADC). The converter is designed based on the Charter 0.18 um processing technology. The design tools used in the project are Cadence Virtuoso schematic editor and Virtuoso Analog Design Environment. Some of the simulation data is analyzed with the assistance of MATLAB.
The dynamic reference ADC is designed to be working under 1.8V supply voltage and takes an input ranging from 0 to 1V. It can achieve an ENOB of 7.5 bits with a sampling rate of 250MHz. The building blocks of the converter include the reference voltage, the comparator and the dynamic voltage reference. The reference voltage block makes use of the current approach mode of bandgap reference and in the dynamic voltage reference, the R2R network is implemented. The current steering DAC structure is applied in the dynamic reference generation block. The comparator used is a CMOS analog comparator without internal clocking. |
|---|