Development of an advanced nano-satellite VELOX-I – study of column-level ADC architectures for high speed CMOS image sensors

• Main Author: Liu, Lifen.
• Other Authors: Chen Shoushun
• Format: Final Year Project
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/54468
• Institution: Nanyang Technological University

This Final Year Project (FYP) is to design a 10-bit Column-Parallel Analog-to-Digital Convertor (ADC) using CMOS technology. This ADC design is used as a part of High Speed CMOS Image Sensors, and this design must be satisfy the requirements of size and speed. The main concern of this design is choosing an applicable architecture to be used in this design application. First of all, there are thousands analog inputting to this ADC from pixel arrays, so this architecture chosen should be good to be handle those big amount inputs in an acceptable time. Secondly, the size of this ADC should also be considered inside as its size should be as small as possible and can be narrow down to fit into the size of each pixel column. This ADC applied to the CMOS Image Sensor can make a significant improvement in power consumption and accuracy of the whole Image Sensor system as ADC convert the analog signal into digital one, which save power for the following process (Read-Out Part) , simplify the process of Read-Out circuit and also improve the accuracy of the whole system. This 12-bit Column-Parallel ADC design is realized on the 65nm GF process, the layout of a Ramp generator was built and the schematic of whole ADC system is simulated.