Exploring algorithmic error tolerrance of circuit simulators
Integrated Circuit (IC) technology is getting more advanced and the number of transistors required for an Integrated Circuit (IC) is increases by a factor of 2 every 18 months. Not only that, the size of the transistor is getting smaller, from few micrometers to current tens nanometers, the...
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sg-ntu-dr.10356-550402023-03-03T20:26:32Z Exploring algorithmic error tolerrance of circuit simulators Lim, Hui Hui. School of Computer Engineering Centre for High Performance Embedded Systems Nachiket Kapre DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling Integrated Circuit (IC) technology is getting more advanced and the number of transistors required for an Integrated Circuit (IC) is increases by a factor of 2 every 18 months. Not only that, the size of the transistor is getting smaller, from few micrometers to current tens nanometers, therefore the increment in transistor complexity and decrement in size of transistor and IC increase the probability of voltage glitches occurrence. This will cause errors in the circuitry since the transistor not to behave as per specification due to these frequent voltage glitches occurrence. The impact to the circuitry can be shown by introducing error inserting. This can be done by simulating circuit benchmarks using two different error insertion algorithms – error insertion by inserting constant error percentage which is to find the approximate range of the error tolerance and bit-flipping algorithm is to find out the actual impact on the result. For simplication, we are focusing on insert error into the matrices. This project aims to ascertain how much error tolerance that a simulator called “Simulation Program with Integrated Circuit Emphasis” (SPICE) can be tolerated. We use SPICE as a case study to analyase the impact of the hardware errors on software behavior. It is shown that error injected into the decomposed matrix is far more dangerous than matrix state before matrix decompostion. It also shows that the maximum error tolerance is less than probability value of 10*e^{−7}. Though the tolerance value is low, in fact, in reality, error does not occur that frequent. Therefore, the simulator is able to tolerate most errors in reality. Bachelor of Engineering (Computer Science) 2013-12-04T08:52:17Z 2013-12-04T08:52:17Z 2013 2013 Final Year Project (FYP) http://hdl.handle.net/10356/55040 en Nanyang Technological University 33 p. application/pdf |
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DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling Lim, Hui Hui. Exploring algorithmic error tolerrance of circuit simulators |
description |
Integrated Circuit (IC) technology is getting more advanced and the number
of transistors required for an Integrated Circuit (IC) is increases by a factor of
2 every 18 months. Not only that, the size of the transistor is getting smaller,
from few micrometers to current tens nanometers, therefore the increment in
transistor complexity and decrement in size of transistor and IC increase the
probability of voltage glitches occurrence. This will cause errors in the circuitry
since the transistor not to behave as per specification due to these frequent
voltage glitches occurrence.
The impact to the circuitry can be shown by introducing error inserting. This
can be done by simulating circuit benchmarks using two different error insertion
algorithms – error insertion by inserting constant error percentage which is to
find the approximate range of the error tolerance and bit-flipping algorithm is
to find out the actual impact on the result. For simplication, we are focusing on
insert error into the matrices.
This project aims to ascertain how much error tolerance that a simulator called
“Simulation Program with Integrated Circuit Emphasis” (SPICE) can be tolerated.
We use SPICE as a case study to analyase the impact of the hardware errors on
software behavior. It is shown that error injected into the decomposed matrix
is far more dangerous than matrix state before matrix decompostion. It also
shows that the maximum error tolerance is less than probability value of
10*e^{−7}.
Though the tolerance value is low, in fact, in reality, error does not occur that
frequent. Therefore, the simulator is able to tolerate most errors in reality. |
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School of Computer Engineering |
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School of Computer Engineering Lim, Hui Hui. |
format |
Final Year Project |
author |
Lim, Hui Hui. |
author_sort |
Lim, Hui Hui. |
title |
Exploring algorithmic error tolerrance of circuit simulators |
title_short |
Exploring algorithmic error tolerrance of circuit simulators |
title_full |
Exploring algorithmic error tolerrance of circuit simulators |
title_fullStr |
Exploring algorithmic error tolerrance of circuit simulators |
title_full_unstemmed |
Exploring algorithmic error tolerrance of circuit simulators |
title_sort |
exploring algorithmic error tolerrance of circuit simulators |
publishDate |
2013 |
url |
http://hdl.handle.net/10356/55040 |
_version_ |
1759853179509407744 |