Design of high performance low-dropout regulators for on-chip applications

• Main Author: Chong, Sau Siong
• Other Authors: Chan Pak Kwong
• Format: Theses and Dissertations
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/55852
• Institution: Nanyang Technological University

The growing portable and battery powered devices have driven the power management circuits to consume as low power as possible so as to prolong the operation life of the devices. Low-dropout (LDO) regulators are important building blocks in power management unit which provides majority or all power sources in a system chip. This work focuses on the circuit design techniques for high-performance regulators for on-chip applications. This thesis presents (i) a new frequency compensation technique for multistage amplifier, (ii) two types of composite power transistor, (iii) a new ultra-low quiescent current regulator architecture and (iv) a new low-impedance loading network circuit design technique for LDO regulator applications. For frequency compensation, the design objectives are to address power-bandwidth-efficiency as well as area-efficiency at a large capacitive load. Turning to the LDO regulator designs, the focuses are to address low quiescent current consumption, low voltage operation, good stability and current efficiency at light loads. A cross feedforward cascode compensation technique is proposed for a three-stage amplifier design. Implemented in 65 nm CMOS technology, the amplifier only consumes a quiescent current of 17 μA at a 1.2 V supply and occupies an active area of 0.0088 mm2. In addition, when driving a 500 pF capacitive load, it achieves a unity-gain bandwidth of 2 MHz with a phase margin of 52°. The proposed amplifier is stabilized by a small compensation capacitor of only 1.15 pF. In view of application as an error amplifier in LDO regulator design, it is particularly useful for driving a power transistor with significant large input capacitance. In another contribution, two types of composite power transistor based regulator are proposed. Due to employment of shunt feedback resistor to reduce impedance in the composite power transistor, the stability criterion is relaxed whereas on-chip compensation capacitor can be reduced to only few pF level. For the first output-capacitorless LDO (OCL-LDO) regulator with push-pull composite power transistor, it can operate at a minimum supply of 0.75 V and supply a maximum load current of 50 mA while consuming only 12.15 μW. It is fabricated in 65 nm CMOS technology and occupies an active area of 0.0096 mm2. The measured output change is 103 mV when load current is switched from 0 to 50 mA in 100 ns at a 100 pF capacitive load. For the second output-capacitor LDO (OC-LDO) regulator with dynamic-biased composite power transistor, it is capable to provide a maximum current of 450 mA from a 1.2 V supply and dissipates only 4.7 μA of quiescent current at zero load current. It is realized and simulated in 0.18 μm CMOS technology. With an output capacitor of 4.7 μF, the simulated output change is 64.62 mV when the load current is changed from 0 to 450 mA in 10 ns. It has shown that both LDO regulators greatly enhance the transient responses with respect to conventional counterparts. Further contribution deals with a new architecture employing adaptive power transistors circuit technique for ultra-low quiescent current OCL-LDO regulator. Depending on the load current, the OCL-LDO regulator transforms itself to a two or three stage configuration automatically. Implemented in 65 nm CMOS process technology, the proposed regulator consumes a quiescent current of 0.9 μA at zero load current. It occupies an active area of 0.017 mm2 and is able to supply a maximum current of 100 mA from a 1.2 V supply. Despite having low quiescent current performance, the transient response is not compromised significantly. The measured output change is 68.8 mV when the load current is switched from 0 to 100 mA in 300 ns with a capacitive load of 100 pF. It is able to recover from transient response within 6 μs. Finally, the introduction of a low-impedance loading network circuit is dedicated to enhance the stability or to improve light-load efficiency. To demonstrate the proposed circuit technique, it is applied to the design of an OCL-LDO regulator. The simulation results have confirmed the circuit operation in 0.18 μm CMOS technology. The simulated quiescent current is 14 μA at a 1.2 V supply, no minimum loading current is required. Therefore, the current efficiency at light load is enhanced. The proposed design technique can be applied to LDO regulator with any structure. All the proposed works in this thesis consume very small quiescent currents whilst having a good balanced performance metrics when compared with the representative prior-art works. It has validated that they are useful for on-chip applications.