Automated circuit diagram generator

• Main Author: Chia, Xueyi
• Other Authors: School of Computer Engineering
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/59009
• Institution: Nanyang Technological University

This project has been motivated by the fact that the engagement of teaching and learning is taking a shift from face to face instructions based in classroom setting to the inclusion of learning that is peer to peer. The main objective of this project is to develop a python program, which input file such as text file/verilog file. The project in question intends to make a program that is capable of performing essential decision-making as well as checking errors. The program will be able to output a TEX/pgf file that is essential for visualization. The project entails the use of common resources which include xilinx, altera ModelSim, Notepad ++, LaTeX, and PyScripter as the software resources and the HP Pavilion g series as the hardware resource. For the program to function well, I shall require file i/o and recognition of keyword. The general architecture of the project will be in three phases: reading input file, analyzing the input file and writing to an output file. The report also discusses the way the project shall be implemented in which there will be two major events to take place. There are the reading of text file using the file i/o and the reading of the verilog file using file i/o. The project shall entail two versions: version 1 and 2. It is under this part that the testing of the project is done and the results highlighted. Furthermore, the constraints of each version are discussed. I notice that there are constraints met by the first version that version 2 finds a solution. The report ends with the suggestion of future works that is needed to make the program work in a wider perspective.