Content analysis on open source hardware designs

• Main Author: Kang, Yu Xun
• Other Authors: School of Computer Engineering
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Computer science and engineering
• Online Access: http://hdl.handle.net/10356/59031
• Institution: Nanyang Technological University

With the ever increasing complexity of circuits design, many problems arises; the most prevalent being design errors. A complex schematic design may contain errors that the user may overlook. Hence, a computer language that can be used to describe the design of the hardware is needed. The Hardware Description Language [1] (HDL) is a unique type of computer language built for describing electronic or digital circuits, an example of which is Verilog. The Verilog code consists of modules and the codes within these modules are used to describe hardware. Once the HDL is designed and simulated, a program will then convert the HDL code into a piece of hardware to ensure that the design contains no errors. An example of such software is the Xilinx Integrated Software Environment (ISE) [2] tool. The synthesis tool can be used to obtain accurate information such as the total number and types of computational resources, such as adders, registers, multipliers, etc, found in the Verilog code. The downside to using a synthesis tool is the need for implementation. In the Xilinx tool [2], there are 3 processes, synthesis, implementation and generate programming.. A Verilog code will need to go through all 3 processes, which may take a long time. Hence, a program could be created such that it is able to provide users a means to predict the computational resources from a Verilog code without having to go through the processes in the synthesis tool. However, it should be noted that the parser cannot fully replace the synthesis tool in terms of obtaining complete data from the Verilog codes. This project aims to create a parser coded using the python language to extract high level information from the code, that describes the hardware, from within the Verilog file, and check how close the generated result would be as compared to the result generated by the Xilinx tool. Information is extracted from the codes, which describes hardware, such as the ports and signals, their width length, and also the total number of registers, arithmetic operators and logical operators. In this report, the project life cycle, including the planning, implementation and testing, as well as the obtained results will be discussed.