Programmable divide-by-n counter for RFIC

• Main Author: Qi, Wen
• Other Authors: Boon Chirn Chye
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/60183
• Institution: Nanyang Technological University

Phase-locked loop is the most widely used module in the latest generation communication systems. It can be used to synthesize frequency. One of the important blocks in a frequency synthesizer is the frequency divider. Programmable divide-by-N counter is one of the integer frequency dividers, which enables the capability of division ratio selection but works at relative high frequency. In this report, a synchronous 3-stage programmable divide-by-N frequency divider using 65 nm CMOS technology, suitable for 2.4 GHz ISM band applications was introduced. It is designed to operate at high frequency and consume low power. Simulation results show that this 3-stage programmable divide-by-N counter using 65 nm CMOS process is capable of operating up to 3.2 GHz for a 1 V power supply voltage. And at the target frequency 2.4 GHz, it has power consumption of 0.3251 mW with 1 V power supply voltage.