Group IV nanowire formation and its application
This thesis presents the studies on Group IV nanowire formation and its solar cell application. In the nanowire formation part, firstly large-area arrayed Si and SiGe nanowires with Ge contents of about 16% and 29% were formed by an electrochemical etching method in an HF-AgNO3 aqueous solution. The...
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Format: | Theses and Dissertations |
Language: | English |
Published: |
2014
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Online Access: | http://hdl.handle.net/10356/60572 |
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Institution: | Nanyang Technological University |
Language: | English |
Summary: | This thesis presents the studies on Group IV nanowire formation and its solar cell application. In the nanowire formation part, firstly large-area arrayed Si and SiGe nanowires with Ge contents of about 16% and 29% were formed by an electrochemical etching method in an HF-AgNO3 aqueous solution. Then the effects of Ge on the electrochemical reaction rate and nanowire surface roughness were discussed. Secondly, orderly-arrayed Si and SiGe nanowires were formed by the Au-assisted electrochemical etching method combined with nanosphere lithography. SiGe nanowire heterostructure formation was also presented. In the nanowire-based solar cell application part, two solar cell structures were demonstrated with improved efficiency and in-depth analysis was presented. Firstly, highly folded Si nanowire-based p-i-n junction solar cells were formed by completely filling up the p-type Si nanowire interspaces through an intrinsic Si deposition by the low-pressure chemical vapor deposition system, followed by a phosphorus-containing spin-on-dopant diffusion to form the top n-type layer. Then the light angle of incidence effect was studied. Secondly, arrayed Si nanowire/nanorod-based core-shell p-n junction solar cells were demonstrated. The core-shell p-n junctions were realized by the spin-on-dopant diffusion process to convert the exterior portion of the p-type nanowire into n-type forming core-shell junction. Then the parasitic series resistance effect was analyzed by constructing a circuit model. In addition, nanowire surface roughness and Au contamination, which may be limiting factors for higher efficiency, were discussed. |
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