A study of the electronic properties of III-V compound semiconductor integrated with silicon

• Main Author: Chen, Kah Pin
• Other Authors: Yoon Soon Fatt
• Format: Theses and Dissertations
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Materials
• Online Access: http://hdl.handle.net/10356/60691
• Institution: Nanyang Technological University

This thesis presents systematic studies on monolithic heteroepitaxial integration of III-V compound semiconductor on Si substrate employing the graded Si1-xGex buffer layer. One of the essential growth procedures for antiphase boundary free GaAs/Ge growth is the pre-growth high-temperature in-situ annealing of a Ge surface coupling with the use of a 6o off-cut Si substrate. Besides, a study was performed to examine the impact of various GaAs buffer thicknesses on the electrical characteristics of GaAs grown on the hetero-substrate. Furthermore, an in-depth study of the dependence of electrical characteristics on proximity to the GaAs/Ge heterointerface was performed using deep-level transient spectroscopy analysis. Lastly, AlGaAs/GaAs heterojunction bipolar transistors were grown on the Ge/graded-Si1-xGex/Si hetero-substrate to demonstrate the viability of this integrated platform. A correlation between the DC characteristics, especially offset voltage and deep-level traps behavior in the GaAs layer, were discussed.