Design and analysis of temperature-variation-tolerant ultra-low voltage circuits for wireless sensor nodes

• Main Author: Phua, Isabel Jie Wei
• Other Authors: School of Electrical and Electronic Engineering
• Format: Final Year Project
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering
• Online Access: http://hdl.handle.net/10356/61409

Memory arrays are an essential building block in any digital system. SRAM is a device that has infiltrate into myriads of hardware systems, acting as an important component. The designing of an SRAM is very critical to designing other digital circuits as well. Memory dominates the majority of space in an integrated circuit. SRAM design comprises of prime considerations such as improved speed and condensed layout area. This paper presents the basics of SRAM which includes the operations and the design of a 1 Kb SRAM in the 65 nm CMOS process. The aim of this project was to build a 1Kb SRAM cell array design and to learn how the SRAM array functions. Drawing and simulation was done using EDA (Electronic design automation) tools such as Cadence Virtuoso, using the UMC65nm technology. Final test results verify the function of the SRAM. The designed SRAM can be used in ultra-low-power SoCs.