Design of low-voltage differential signaling (LVDS) system
This Report presents a Low Voltage Differential Signaling (LVDS) standard circuit driver and receiver. Circuit Driver is designed under supply voltage of 1.8V. Circuit Driver is implemented using 180nm CMOS technology. Driver circuit uses nominal current of 3.5mA, produced a voltage swing of 350...
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| 主要作者: | |
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2014
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/61434 |
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| 機構: | Nanyang Technological University |
| 語言: | English |