A scalable and compact linear solver with a focus on model predictive control
Systolic Array architectures are data-flow based but designing architectures for solving specific problems can pose a challenge. In this thesis, an investigation into a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition is presented. A n...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2014
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| 在線閱讀: | https://hdl.handle.net/10356/61839 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Systolic Array architectures are data-flow based but designing architectures for solving specific problems can pose a challenge. In this thesis, an investigation into a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition is presented. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. The proposed linear solver has a throughput of approximately 1 million linear systems per second for matrices of size N = 4 and approximately 82 thousand linear systems per second for matrices of size N = 16. In comparison with similar work, the proposed design offers up to a 12x improvement in speed whilst requiring up to 50% fewer hardware resources. As a result, a linear system of size N = 64 can now be implemented on a single FPGA, whereas previous work was limited to N = 12 and resorted to complex multi-FPGA architectures to achieve the same effect. Moreover, the scalable design can be adapted to different sized problems with minimum effort. |
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