A scalable and compact linear solver with a focus on model predictive control

Systolic Array architectures are data-flow based but designing architectures for solving specific problems can pose a challenge. In this thesis, an investigation into a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition is presented. A n...

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Main Author: Ong, Kevin Shen Hoong
Other Authors: Suhaib A. Fahmy
Format: Theses and Dissertations
Language:English
Published: 2014
Subjects:
Online Access:https://hdl.handle.net/10356/61839
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-618392023-03-04T00:46:07Z A scalable and compact linear solver with a focus on model predictive control Ong, Kevin Shen Hoong Suhaib A. Fahmy Ling Keck Voon School of Computer Engineering Centre for High Performance Embedded Systems DRNTU::Engineering::Computer science and engineering::Computer systems organization::Special-purpose and application-based systems DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures DRNTU::Engineering::Computer science and engineering::Hardware::Control structures and microprogramming DRNTU::Engineering::Computer science and engineering::Hardware::Logic design Systolic Array architectures are data-flow based but designing architectures for solving specific problems can pose a challenge. In this thesis, an investigation into a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition is presented. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. The proposed linear solver has a throughput of approximately 1 million linear systems per second for matrices of size N = 4 and approximately 82 thousand linear systems per second for matrices of size N = 16. In comparison with similar work, the proposed design offers up to a 12x improvement in speed whilst requiring up to 50% fewer hardware resources. As a result, a linear system of size N = 64 can now be implemented on a single FPGA, whereas previous work was limited to N = 12 and resorted to complex multi-FPGA architectures to achieve the same effect. Moreover, the scalable design can be adapted to different sized problems with minimum effort. MASTER OF ENGINEERING (SCE) 2014-11-06T02:29:40Z 2014-11-06T02:29:40Z 2014 2014 Thesis Ong, K. S. H. (2014). A scalable and compact linear solver with a focus on model predictive control. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/61839 10.32657/10356/61839 en 127 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Computer science and engineering::Computer systems organization::Special-purpose and application-based systems
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
DRNTU::Engineering::Computer science and engineering::Hardware::Control structures and microprogramming
DRNTU::Engineering::Computer science and engineering::Hardware::Logic design
spellingShingle DRNTU::Engineering::Computer science and engineering::Computer systems organization::Special-purpose and application-based systems
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
DRNTU::Engineering::Computer science and engineering::Hardware::Control structures and microprogramming
DRNTU::Engineering::Computer science and engineering::Hardware::Logic design
Ong, Kevin Shen Hoong
A scalable and compact linear solver with a focus on model predictive control
description Systolic Array architectures are data-flow based but designing architectures for solving specific problems can pose a challenge. In this thesis, an investigation into a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition is presented. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. The proposed linear solver has a throughput of approximately 1 million linear systems per second for matrices of size N = 4 and approximately 82 thousand linear systems per second for matrices of size N = 16. In comparison with similar work, the proposed design offers up to a 12x improvement in speed whilst requiring up to 50% fewer hardware resources. As a result, a linear system of size N = 64 can now be implemented on a single FPGA, whereas previous work was limited to N = 12 and resorted to complex multi-FPGA architectures to achieve the same effect. Moreover, the scalable design can be adapted to different sized problems with minimum effort.
author2 Suhaib A. Fahmy
author_facet Suhaib A. Fahmy
Ong, Kevin Shen Hoong
format Theses and Dissertations
author Ong, Kevin Shen Hoong
author_sort Ong, Kevin Shen Hoong
title A scalable and compact linear solver with a focus on model predictive control
title_short A scalable and compact linear solver with a focus on model predictive control
title_full A scalable and compact linear solver with a focus on model predictive control
title_fullStr A scalable and compact linear solver with a focus on model predictive control
title_full_unstemmed A scalable and compact linear solver with a focus on model predictive control
title_sort scalable and compact linear solver with a focus on model predictive control
publishDate 2014
url https://hdl.handle.net/10356/61839
_version_ 1759853961061335040