Design and analysis of multi-channel ultra-low noise ultra-low energy bio-potential neural recording circuits and systems

• Main Author: Han, Dong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Theses and Dissertations
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: http://hdl.handle.net/10356/61873
• Institution: Nanyang Technological University

Neural-to-electronic interfaces are essential methods for neuroscience and neural prosthetics to monitor and stimulate central nerve system. The noisy application environments, high channel density and stringent thermal budget demand the interfaces with ultra-low input referred noise and ultra-low power dissipation. Conventional complementary metal-oxide-semiconductor interfacing circuits and systems have either high input referred noise or high power consumption due to the noise-power-dynamic range trade-off. In system level, this research proposed a neural recording architecture with two-level power supply scheme and dynamic range folding technique. This architecture can efficiently break the noise-power-dynamic range trade-off and achieve 53% power reduction without degrading the input referred noise, bandwidth and overall dynamic range performances. The multiplexing before variable gain amplifier structure and two-branch pipeline dynamic range folding sampling and holding (S/H) network achieve a buffer-less multi-channel neural recording system and result in 28% area saving. In circuit level, the low noise amplifier uses current reuse technique to improve input transconductance and achieve low noise efficiency factor. The variable gain amplifier has two-level power supply to reduce power consumption with high output swing. The pre-most significant bit determination and double-side self-aligned successive approximation register control logic save both area and power consumption. Benefiting from the proposed system and circuit level techniques, this research delivered a high performance silicon prototype neural recording chip with 100-channel recording capacity, 3.2 μVrms input referred noise, 0.94 μW/channel power consumption and 8.27-bit effective resolution.