Analysis and design of audio class D amplifiers

• Main Author: Guo, Linfei
• Other Authors: Chang Joseph Sylvester
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits; DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/62946
• Institution: Nanyang Technological University

Design and Analysis of Audio Class D Amplifiers Abstract Class-D Amplifiers (CDAs) are at this juncture widely accepted over their linear counterparts due to their higher power-efficiency and their ensuing smaller form factor, and the design art thereto is relatively mature. Nevertheless, despite their maturity, the electronics industry desires CDAs with substantially improved specifications, including higher linearity (often qualified by Total Harmonic Distortion + Noise (THD+N) and Intermodulation Distortion (IMD)) and higher immunity to supply noise (often qualified by Power Supply Rejection Ratio (PSRR) and Power Supply induced Intermodulation (PS-IMD)). The broad objective of this Ph.D. program is to design CDAs with said improved specifications – on the basis of analytical investigations (into the mechanisms of and the circuit parameters affecting the various specifications of CDAs) and design and monolithic realization of CDA prototypes (embodying novel architectures and/or circuits). The specific CDA architectures of interest are the somewhat esoteric ultra-low-power Bang-bang Control CDAs (appropriate for power-critical wearable devices) and the ubiquitous Pulse-Width-Modulation (PWM) CDAs (appropriate for general audio applications). A number of contributions are made herein. First, to improve the linearity of Bang-bang control CDAs, their IMD is analytically investigated to ascertain the mechanisms thereto and to derive expressions to analytically model the IMD; it is interesting that despite its imperativeness, the IMD of Bang-bang CDAs remains unreported/uninvestigated in literature. From our analysis, we observe the interesting phenomenon of the presence of even-order IMD that is usually negligible/unreported in CDAs (and in linear amplifiers); as expected, odd-order IMD is also present. We show that in some practical scenarios, the even-order IMD can be unexpectedly dominant over the odd-order IMD. The derived analytical expressions for the IMD are verified by simulations and on the basis of measurements on a physical CDA. This analysis is insightful and useful as it provides an analytical basis to model the IMD of Bang-bang CDAs, hence their linearity, and delineates the possible trade-offs in relation to other imperative parameters (e.g. PSRR) to mitigate the IMD. Second, to improve both the linearity and the supply noise immunity of PWM CDAs, a novel PWM CDA design is proposed and a fully-integrated prototype CDA (65nm CMOS) realized. The proposed design, embodying a novel carrier generator and the first-ever ‘phase-error-free’ PWM modulator, circumvents the otherwise undesirable trade-offs in conventional designs that involve linearity and noise immunity (and power-efficiency and Electromagnetic Interference, EMI). On the basis of measurements on the prototype CDAs, the proposed design achieves not only the highest PSRR reported to-date, but also the highest Figures-of-Merit (FOMs) when benchmarked against reported state-of-the-art CDAs. Third, we identify that the ground-bounce in CDAs can drastically degrade the linearity (and reliability) of CDAs (all CDAs including the Bang-bang and PWM CDAs). Interestingly, this phenomenon has not been analytically investigated/reported in literature, and the means for its mitigation are largely empirical. We complete the first-ever analytical investigation to ascertain the mechanisms of and the circuit parameters affecting the ground bounce, and its effects on CDAs. We show that the generally-accepted and/or intuitive ‘knowhow’ for mitigating ground bounce may unexpectedly exacerbate ground bounce – the effect is instead the converse and adverse. On the basis of this investigation, we propose a complete design methodology to reduce the ground-bounce and its effects on CDAs, and further propose a ground-bounce-aware dead-time circuit design to mitigate the ground bounce effects. The efficacy of the proposed design methodology and proposed dead-time circuit are verified by means of measurements and simulations. Specifically, a PWM CDA optimized with said methodology and embodying said dead-time circuit features significantly higher linearity (4 times lower THD) compared to the same CDA without said optimization and embodiment.