IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process
Develop a detailed description of a post assembly IC manufacturing process from the five different views using the IDEF* methodology namely function, information, process, resource and organisation.
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sg-ntu-dr.10356-63762023-03-11T17:17:07Z IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process Sim, Alvin Chin Beng. Ang, Cheng Leong School of Mechanical and Production Engineering DRNTU::Engineering::Manufacturing::Production management Develop a detailed description of a post assembly IC manufacturing process from the five different views using the IDEF* methodology namely function, information, process, resource and organisation. Master of Science (Computer Integrated Manufacturing) 2008-09-17T11:13:16Z 2008-09-17T11:13:16Z 2004 2004 Thesis http://hdl.handle.net/10356/6376 Nanyang Technological University application/pdf |
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DRNTU::Engineering::Manufacturing::Production management Sim, Alvin Chin Beng. IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
description |
Develop a detailed description of a post assembly IC manufacturing process from the five different views using the IDEF* methodology namely function, information, process, resource and organisation. |
author2 |
Ang, Cheng Leong |
author_facet |
Ang, Cheng Leong Sim, Alvin Chin Beng. |
format |
Theses and Dissertations |
author |
Sim, Alvin Chin Beng. |
author_sort |
Sim, Alvin Chin Beng. |
title |
IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
title_short |
IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
title_full |
IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
title_fullStr |
IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
title_full_unstemmed |
IDEF* modeling of a post-assembly IC (Integrated Circuit) manufacturing process |
title_sort |
idef* modeling of a post-assembly ic (integrated circuit) manufacturing process |
publishDate |
2008 |
url |
http://hdl.handle.net/10356/6376 |
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1761781444252794880 |