High switching-frequency DC-DC converter IC layout

• 主要作者: Neo, Yang Yee
• 其他作者: Victor Adrian
• 格式: Final Year Project
• 語言: English
• 出版: 2015
• 主題: DRNTU::Engineering::Electrical and electronic engineering
• 在線閱讀: http://hdl.handle.net/10356/64151

This report pertains to the layout design of building blocks of a high switching-frequency DC-DC converter. The building blocks are an on-chip LC filter (inductor and capacitor), comparator, and an Analog-to-Digital Converter (ADC). The layout design is optimized for small area and high performance. For the on-chip capacitor, we investigate the different kind of capacitor layout methodologies. Two suitable capacitors are proposed and designed to achieve higher capacitance per unit area. The various uses of decoupling and coupling capacitors in layout design are implemented in the layout to improve the circuit's overall performance by filtering high frequency noise and at the same time preventing DC signal from grounding and/or to block DC signals. For the on-chip inductor, we implement a proposed “double stack” spiral inductor to obtain an even higher inductance within the same area as compared to that without the proposed double stack. The spiral inductor is designed on the basis of all of the available six metal layers and the spiral inductor models available in CMOS 0.18m technology. For the comparator and the ADC, a bottom-up approach is employed in the layout design. Various mixed-signal and “non-conventional” layout techniques are used to layout the ADC. The area as well as the parasitic capacitance and resistance are reduced drastically, thereby improving the performance. The design of the basic cell that is layout using the conventional and non-conventional methodologies shows an area reduction from 5.94m x 5.84m to 4.62m x 5.84m, whereas the parasitic capacitance is reduced from 830 fF to 265 fF. The physics in achieving these significant area and parasitic reductions are also studied and discussed upon.