Class-D amplifier power stage with PWM feedback loop

• Main Author: Lam, Chun Kit
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/64272
• Institution: Nanyang Technological University

The introduction of the Class-D power amplifier concept has made a revolutionary impact on today’s mobile audio power amplifier industry. This is simply due to its ultra-high power efficiency, which allows longer battery life and smaller heat sinks to be used. The basic open-loop Class-D power amplifier is composed of a pulse modulator, an output power stage, a passive LC low pass filter, and a speaker load. The pulse modulator quantizes the input audio signal into a single-bit high frequency pulse signal. Depending on the implementation of the pulse modulation stage, the Class-D power amplifier can be designed to amplify either analog or digital audio signal efficiently. This is very desirable in the modern trend of audio amplifier market due to the evolutionary development in both digital signal processing as well as the digital storage technology. With digital Class-D amplifier, a fully digital audio amplifier solution is made possible. Regrettably, the lack of rejection to power supply noise has always been a major drawback for a basic open-loop Class-D power amplifier. Fortunately, negative feedback loop can be implemented in the Analog Class-D power amplifier to mitigate such problem efficiently and effectively. However, such technique is not very efficient for fully digital Class-D implementation due to the circuit complexity. In order to relax the design complexity in digital Class-D solution, an open-loop topology is preferred. The power supply noise can be mitigated by applying a negative feedback loop locally around the output stage. This thesis proposes a Second-Order direct Pulse Width Modulation (PWM) negative feedback loop for any open-loop PWM Class-D amplifiers with single ended output stage. The proposed design uses GLOBALFOUNDRIES’ (GF’s) 0.18μm CMOS technology. The fabricated chip was measured and it achieves a practical measurement of greater than 80 dB supply noise rejection. The linearity of the proposed design is reflected by its Total Harmonic Distortion (THD) results which is smaller than 0.04% at a 1 kHz sinusoidal test signal. In addition, a very detailed time domain analysis which quantifies the inherent distortion from the proposed PWM feedback loop is performed.