Design of CMOS dynamic reference ADC
A low power 8-bit dynamic reference ADC is presented. This ADC is designed based on the Charter 0.18μm technology and the circuit is designed in Cadence Virtuoso schematic editor and simulated in Virtuoso Analog Design Environment. MATLAB is also needed for data analysis. The dynamic reference ADC i...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2015
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| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/64697 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | A low power 8-bit dynamic reference ADC is presented. This ADC is designed based on the Charter 0.18μm technology and the circuit is designed in Cadence Virtuoso schematic editor and simulated in Virtuoso Analog Design Environment. MATLAB is also needed for data analysis. The dynamic reference ADC is asynchronous and comprises of comparator, R-2R resistive network and voltage reference. It employs binary search algorithm to significantly reduce the number of comparators needed and hence only 8 comparators are needed for 8-bit ADC. The comparator is high speed and has a hysteresis window of 1mV. The voltage reference uses the current mode approach bandgap circuit and has a temperature coefficient of 15.2ppm/K. The dynamic reference is generated by a built-in current steering DAC which consists of the voltage reference and the R-2R resistive network. The dynamic reference ADC is designed to operate under 1V power supply and have an input range of 0-600mV. It achieves a 41.875dB signal-to-noise-plus-distortion (SNDR) and ENOB of 6.43 bits with a sampling rate of 200kHz. |
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