Design of security primitives for trustworthy integrated circuits
The horizontal business model in semiconductor industry has brought economic benefits but relinquished the control that integrated circuit (IC) designer had in chip design and manufacturing, thus making chips expose to greater security threats and vulnerable to various kinds of hardware attacks. As...
Saved in:
Main Author: | |
---|---|
Other Authors: | |
Format: | Theses and Dissertations |
Language: | English |
Published: |
2015
|
Subjects: | |
Online Access: | https://hdl.handle.net/10356/65631 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Institution: | Nanyang Technological University |
Language: | English |
Summary: | The horizontal business model in semiconductor industry has brought economic
benefits but relinquished the control that integrated circuit (IC) designer had
in chip design and manufacturing, thus making chips expose to greater security
threats and vulnerable to various kinds of hardware attacks. As electronic devices
becoming increasingly ubiquitous and permeated into our daily lives, critical basic
infrastructures and national defense systems, hardware security features that
can assure the trustworthiness of an integrated system in a reliable, efficient and
inexpensive way are highly desirable. In the dissertation, two embedded hardware
security primitives, namely active current sensors and Physical Unclonable
Functions (PUFs) are investigated for hardware Trojan (HT) detection, device
identification and authentication.
Hardware Trojans are the deliberate and malicious alterations to original IC designs
that can jeopardize the design integrity, stealing the confidential information
or paralyzing the system connected to the subverted chip upon their activation.
In this thesis, a transient power supply current sensor to facilitate the screening
of an IC for HT infection is proposed. Based on the power gating scheme, it converts
the current activity on local power grid into a timing pulse from which the
timing and power related side channel signals can be externally monitored by the
existing scan test architecture. Its current comparator threshold can be adjusted
for calibration against the quiescent current noise floor to reduce the impacts
of process variations. Post-layout statistical simulations of process variations are
performed on the ISCAS’85 benchmark circuits to demonstrate the effectiveness
of the proposed technique for the detection of delay-invariant and rarely switched
i
HTs. Compared with the detection error rate of a 4-bit counter based HT reported
by an existing HT detection method using the path delay fingerprint, the proposed
method shows an order of magnitude improvement in the detection accuracy.
Physical Unclonable Functions are emerging security primitives that are useful
in secure key generation, device authentication, and counterfeit detection and prevention.
This thesis presents two main contributions in PUF research community:
1) An ultra-low power and small footprint hybrid RO PUF with very high temperature
stability is proposed as an ideal candidate for lightweight applications.
The classic ring oscillator (RO) based PUF is resilient to noise impacts, but its
response is susceptible to temperature variations. Additional components or complex
algorithms are usually employed to address this problem at the expense of
large area and power consumption overheads. The proposed PUF exploits the negative
temperature coefficient property and the low-power subthreshold operation
of current starved inverters to mitigate the variations of differential RO frequencies
with temperature. The new architecture uses conspicuously simplified circuitries
to generate and compare a large number of pairs of RO frequencies, and facilitate
logical reconfigurability to thwart machine learning attacks. The proposed
9-stage hybrid RO PUF was fabricated using 65 nm CMOS technology. Its measured
challenge-response pairs (CRPs) possess larger entropy per unit area than
the classic RO PUF design. The PUF occupies only 250 m2 of chip area and
consumes only 32.3 V per CRP at 1.2 V and 230 MHz. The measured average
and worst-case reliabilities of its responses are as high as 99.84% and 97.28%, respectively
over a wide range of temperature from −40 ◦C to 120 ◦C. 2). Another
new low-cost CMOS image sensor based PUF is also proposed. It targets a variety
of security, privacy and trusted protocols that involve image sensor as a trusted
entity. The proposed PUF exploits the intrinsic imperfection during the image
sensor manufacturing process to generate a rich set of unique and stable digital
signatures. The proposed differential readout algorithm stabilizes the response
bits extracted from the random fixed pattern noise (FPN) of selected pixel pairs
determined by the applied challenge against supply voltage and temperature variations.
The threshold of difference can be tightened to winnow out more unstable
response bits from the huge challenge-response space offered by modern image sensors
to enhance the reliability under harsher operating conditions or it can also be
loosened to improve its resiliency against masquerade attacks in routine operating
environment. Experimentations conducted on a 64×64 image sensor fabricated in
180 nm 3.3 V CMOS technology demonstrated that robust and reliable challengeresponse
pairs can be generated with a uniqueness of 49.37% and a reliability of
99.10% under temperature variations of 15∼115 ◦C and supply voltage variations
of 3∼3.6 V. |
---|