Machine learning on FPGA CAD
Parameter tuning for field-programmable gate array (FPGA) computer-aided design (CAD) tools was a difficult task. Plunify proposed a novel solution by incorporating machine learning. A classifier was built and refined iteratively from CAD run records; and it was used to predict whether a new set of...
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| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2015
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| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/65738 |
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| 總結: | Parameter tuning for field-programmable gate array (FPGA) computer-aided design (CAD) tools was a difficult task. Plunify proposed a novel solution by incorporating machine learning. A classifier was built and refined iteratively from CAD run records; and it was used to predict whether a new set of parameters would produce a good design. The machine learning routine has been proven effective; and this paper is an extension aimed to improve performance of the method. We experimented with feature selection and discovered only about 10-20 parameters in the group of 60 were relevant. We also constructed ensemble classifiers that helped to drive Area Under Curve (AUC) score from 0.75 to 0.79; and we further pushed the number to 0.82 when combining ensemble learning and feature selection. |
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