Time mode analog-to-digital converter

Fully digital Analog-to-Digital Converter (ADC) and digitally assisted ADC has gained popularity in recent research works. The continuous scaling in CMOS technology has prompted designers to look for ADC architecture that is highly digital intensive with minimal analog circuitry. Time Mode ADC appea...

Full description

Saved in:
Bibliographic Details
Main Author: Hor, Hon Cheong
Other Authors: Siek Liter
Format: Theses and Dissertations
Language:English
Published: 2016
Subjects:
Online Access:https://hdl.handle.net/10356/65978
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-65978
record_format dspace
spelling sg-ntu-dr.10356-659782023-07-04T17:23:52Z Time mode analog-to-digital converter Hor, Hon Cheong Siek Liter School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering Fully digital Analog-to-Digital Converter (ADC) and digitally assisted ADC has gained popularity in recent research works. The continuous scaling in CMOS technology has prompted designers to look for ADC architecture that is highly digital intensive with minimal analog circuitry. Time Mode ADC appears as an attractive solution due to its more digital intensive topology. As transistor’s gate delay reduces along with scaling in CMOS technology, the resolution and speed of Time Mode ADC also improve along with the advancement in modern CMOS technology. There are two popular types of Time Mode ADC, namely the Voltage-Controlled-Oscillator (VCO) based ADC and the Integrating ADC. The VCO-based ADC works by first converting analog input voltage to frequency/time information by a VCO, where the frequency/time information is subsequently converted to digital code using a time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottleneck for Time Mode VCO- based ADC. In the first part of this research work, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. The main idea of K-locked-loop is to use local feedback in the voltage-time domain for VCO nonlinearity suppression. To the best of the author’s knowledge, this is the first ever proposed feedback system in the voltage-time domain. A 10-bit, 2MS/s K-locked-loop VCO ADC has been modeled using SIMULINK tool in Matlab as a proof of concept. In addition, an AMS model is constructed to further verify the concept of K-locked-loop at the transistor level. Through analysis, the non-ideal effect will be discussed in this thesis. MASTER OF ENGINEERING (EEE) 2016-02-11T08:28:43Z 2016-02-11T08:28:43Z 2016 Thesis Hor, H. C. (2016). Time mode analog-to-digital converter. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/65978 10.32657/10356/65978 en 107 p. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering
spellingShingle DRNTU::Engineering::Electrical and electronic engineering
Hor, Hon Cheong
Time mode analog-to-digital converter
description Fully digital Analog-to-Digital Converter (ADC) and digitally assisted ADC has gained popularity in recent research works. The continuous scaling in CMOS technology has prompted designers to look for ADC architecture that is highly digital intensive with minimal analog circuitry. Time Mode ADC appears as an attractive solution due to its more digital intensive topology. As transistor’s gate delay reduces along with scaling in CMOS technology, the resolution and speed of Time Mode ADC also improve along with the advancement in modern CMOS technology. There are two popular types of Time Mode ADC, namely the Voltage-Controlled-Oscillator (VCO) based ADC and the Integrating ADC. The VCO-based ADC works by first converting analog input voltage to frequency/time information by a VCO, where the frequency/time information is subsequently converted to digital code using a time-to-digital converter. Although high speed high resolution time-to-digital converters are currently available, the inherent nonlinear property of VCO however has become the bottleneck for Time Mode VCO- based ADC. In the first part of this research work, a new concept named K-locked-loop is proposed to solve the nonlinearity issue of VCO within a time mode ADC. The main idea of K-locked-loop is to use local feedback in the voltage-time domain for VCO nonlinearity suppression. To the best of the author’s knowledge, this is the first ever proposed feedback system in the voltage-time domain. A 10-bit, 2MS/s K-locked-loop VCO ADC has been modeled using SIMULINK tool in Matlab as a proof of concept. In addition, an AMS model is constructed to further verify the concept of K-locked-loop at the transistor level. Through analysis, the non-ideal effect will be discussed in this thesis.
author2 Siek Liter
author_facet Siek Liter
Hor, Hon Cheong
format Theses and Dissertations
author Hor, Hon Cheong
author_sort Hor, Hon Cheong
title Time mode analog-to-digital converter
title_short Time mode analog-to-digital converter
title_full Time mode analog-to-digital converter
title_fullStr Time mode analog-to-digital converter
title_full_unstemmed Time mode analog-to-digital converter
title_sort time mode analog-to-digital converter
publishDate 2016
url https://hdl.handle.net/10356/65978
_version_ 1772825233947885568