Design of low power PLL synthesizer for 60 GHz applications

• Main Author: Mahalingam, Nagarajan
• Other Authors: Yeo Kiat Seng
• Format: Theses and Dissertations
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: http://hdl.handle.net/10356/66322
• Institution: Nanyang Technological University

The 60 GHz unlicensed band has attracted both the industry and researchers worldwide in realizing applications with multi giga-bits-per-second (Gbps) data rates. The advancement in integrated circuit (IC) design technology has further enabled the circuit designers to fully integrate the circuits for 60 GHz application on silicon. Also, the increased usage of handheld and smart devices requires the power consumption to be as low as possible. This thesis is part of one such effort to design a 60 GHz system-on-chip (SOC) with low power consumption. In particular, in this thesis, the design of phase-locked loop (PLL) frequency synthesizer, henceforth PLL synthesizer which is a critical component in the 60 GHz transceiver is presented. An important step in the design of PLL synthesizers for 60 GHz application is the identification of bottle-necks in the system architecture and individual circuit blocks especially in the high frequency front-end components. In the first part, this work reviews the 60 GHz system requirements and architecture for the PLL synthesizer. Based on the analysis, the system specifications are derived for the PLL synthesizer and the individual circuit blocks. The front-end components: voltage controlled oscillator (VCO) and first stage high frequency divider are critical sub-system in the PLL synthesizer. Therefore, new circuit design techniques with the multi-coupled LC tanks are adopted in the VCO and the high frequency divider to achieve a wide operational frequency range, low phase noise and high power added efficiency with low power consumption simultaneously. The circuit blocks employing multi-coupled LC tanks is analyzed theoretically and verified experimentally. The VCO implemented with triple-coupled LC tanks achieves a tuning range greater than 15% with a phase noise better than -104 dBc/Hz at 1 MHz offset over the entire operational frequency band. In the high frequency divider, the multi-coupled LC tank is employed to achieve a wide operational locking range with low injected power levels. In the second part, the design and implementation of low frequency blocks in the PLL synthesizer is presented. The divider chain in the PLL synthesizer can support both integer and fractional division ratios to support different reference frequencies based on cost and application requirement. To reduce the non-idealities and complement the PLL synthesizer functionality, improved circuit topologies are introduced in the phase frequency detector (PFD) and charge pump. The PLL synthesizer in this work is implemented in Tower Jazz 0.18μm SiGe BiCMOS process. The fully integrated PLL synthesizer for the 60 GHz application operates in the K-band dissipating a power of 42 mW from 1.8 V supply voltage. The 3rd order external loop filter is used in the PLL synthesizer.