Machine learning on the output of quartus opencl compiler
OpenCL-based high-level synthesis framework is getting popular to used for pro- gramming FPGA as a number of commerical and research frameworks announced. We can improve the tuning of OpenCL compiler by predicting which pragma can improve the utilization of FPGA board such as ALUTs, DSP Blocks, Kern...
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| Format: | Final Year Project |
| Language: | English |
| Published: |
2016
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| Online Access: | http://hdl.handle.net/10356/66506 |
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| Institution: | Nanyang Technological University |
| Language: | English |
| Summary: | OpenCL-based high-level synthesis framework is getting popular to used for pro- gramming FPGA as a number of commerical and research frameworks announced. We can improve the tuning of OpenCL compiler by predicting which pragma can improve the utilization of FPGA board such as ALUTs, DSP Blocks, Kernel Fmax, Logic Utilization, Memory Bits, RAM Blocks and Registers. Currently, only four pragmas, num simb work items, num compute units, work group size and unrolling, are tweaked and run on CHO benchmarks. Three benchmarks, dfadd, dfsin and dfmul are run and the output from OpenCL compiler for those benchmarks are learnt by using machine learning. NeuralNetwork classifier per- formed well among other classifiers for the classification of ALUTs, DSP Blocks, Logic Utilization, Memory Bits and Registers with the average AUC score of 0.95. For classifying Kernel Fmax and RAM Blocks, Bagging and LogitBoosting classifer performed the best and they are close to one another with the average AUC score of 0.97 and 0.96 respectively. |
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