High-speed memory encryption-decryption in embedded systems

• Main Author: Lim, Qi Wei
• Other Authors: Lam Siew Kei
• Format: Final Year Project
• Language: English
• Published: 2016
• Subjects: DRNTU::Engineering::Computer science and engineering::Data::Data encryption
• Online Access: http://hdl.handle.net/10356/66612
• Institution: Nanyang Technological University

This report is part of a follow-up of a project completed in 2015 that involved memory authentication using Tamper Evident Counter (TEC) trees that was implemented on a NIOS II soft processor on a Cyclone II FPGA. This report focusses on the optimisation of the Advanced Encryption Standard (AES) cipher as implemented in the previous project; the algorithm is analysed and the AddRoundKey and MixColumns steps are modified. The implementation is unchanged otherwise – the key size, block size and block cipher mode are fixed at 128 bits, 128 bits and Counter (CTR) mode respectively. A series of tests are conducted to quantify the performance improvement of the optimised versions over the baseline. Performance counters are used to measure the time and clock cycles taken for the program to process a specified number of plaintexts. The results are then tabulated and compared to determine their relative effectiveness. The results show that for this particular implementation, streamlining the flow of data by reducing the number of accesses has a significant impact on the execution speed: aes_optimised, a version of the cipher with only the modified AddRoundKey function, is about 171% faster than the baseline at all tested sample sizes. However, further optimisations in the form of pre-computed T-tables only resulted in another 16.9% performance increase. These findings suggest that optimising the data flow may be a viable option as well.