Profiling a multi-core (Freescale P4080)
Multi-cores can be seen in almost every device out there in the world today. Yet, this processor architecture has yet seen its widespread implementation in safety-critical systems such as the automotive and aerospace industries. Many researchers have tried to theoretically show that multi-cores demo...
Saved in:
| 主要作者: | |
|---|---|
| 其他作者: | |
| 格式: | Final Year Project |
| 語言: | English |
| 出版: |
2016
|
| 主題: | |
| 在線閱讀: | http://hdl.handle.net/10356/66756 |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | Multi-cores can be seen in almost every device out there in the world today. Yet, this processor architecture has yet seen its widespread implementation in safety-critical systems such as the automotive and aerospace industries. Many researchers have tried to theoretically show that multi-cores demonstrate unpredictability in their execution through analysis of the multi-core architecture. This project aims to be able to substantiate such claims that shared resources which include shared cache, memory interconnects and main memory would create contention in these resources and result in un-deterministic execution times. We will be exploring the use of a hypervisor to securely and robustly partition a multi-core system and try to emulate Asymmetric Multiprocessing (AMP) implementations. Our findings show that multi-cores may yet be adequate to support safety-critical applications to meet their real time constraints. |
|---|